Logic Gate Circuit Simulator

Inspectable records

Ledger state

The current ledger marks this instrument verified clean within the source-bound verification corpus.

Area

Mathematics — arithmetic through advanced (algebra, matrices, calculus, sequences/series, number theory, combinatorics, graphing, complex numbers, geometry, logic, sets)

Tranche

tranche-6

Evidence ID

t6-112

Ledger rows

1

No ledger note is attached.

Review findings

The Boolean gate identities are standard and the honest-label restriction to combinational, non-clocked circuits is appropriate. Verdict is NEEDS_REVIEW because gate arity, unknown-net behavior, cycle handling, multiple-driver handling, and propagation-animation semantics are not specified; these omissions prevent unambiguous verification of every claimed simulator behavior.

Formula and scope findings

• The stated gate-by-gate Boolean propagation is the standard method for combinational logic simulation, and AND, OR, NOT, XOR, NAND, and NOR are correctly named, but the specification does not define gate arity or whether XOR means two-input XOR or parity XOR for more than two inputs.
• The netlist semantics are incomplete: behavior for floating inputs, multiple drivers, disconnected outputs, duplicate gate identifiers, and cyclic wiring is unspecified.
• Propagation animation is claimed, but no delay model, event-order rule, or stable-output definition is specified. The Boolean equations alone determine the final combinational value, not animation timing.

Unit assumptions

• Inputs and outputs are Boolean values, represented as 0/false or 1/true; there are no physical units.
• Each listed gate is evaluated from its current input values, and the expected outputs below are the stable values after propagation settles.
• The test circuits use two-input AND, OR, XOR, NAND, and NOR gates, and one-input NOT gates. No multi-input XOR convention is needed in these vectors.

Boundary hardening

BREAK_CLAIMED · SELF_FLAGGED

A cyclic netlist such as a NOT gate whose output is wired to its own input has no stable Boolean result. If accepted without cycle detection, live propagation may oscillate or fail to converge; the simulator should reject it or report undefined output.

Errata and corrections

No applied erratum is attached to this unique-name record.

Inspectable example

4 review vectors are recorded. One source-bound sample is shown below.

{
  "inputs": {
    "circuit": [
      {
        "id": "xor1",
        "gate": "XOR",
        "inputs": [
          "A",
          "B"
        ],
        "output": "X"
      },
      {
        "id": "and1",
        "gate": "AND",
        "inputs": [
          "A",
          "B"
        ],
        "output": "C"
      }
    ],
    "values": {
      "A": 1,
      "B": 0
    },
    "requested_outputs": [
      "X",
      "C"
    ]
  },
  "expected_outputs": {
    "X": 1,
    "C": 0
  },
  "working": "1. XOR gate: X = A XOR B = 1 XOR 0 = 1 because the inputs differ.\n2. AND gate: C = A AND B = 1 AND 0 = 0 because at least one input is 0.\nStable outputs: X = 1, C = 0."
}

Related workflows

No source-defined multi-instrument workflow membership is recorded.

Sources and evidence

These pointers bind the page to evidence. They do not grant authority or collapse verification into deployment.

• VERIFIED_LEDGER.json · VERIFIED_CLEAN
• evidence-tranche6/tranche6-results.json
• BOUNDARY_HAZARD_CATALOG.json